A Low-Spur Current-Biasing-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation

This paper describes a low-voltage fractional-N hybrid phase-locked loop (HPLL) architecture that does not require current biasing. A hybrid loop control with a digital integral path and an analog proportional-gain path offers technology scalability as well as linear phase detection. The analog control path consists of a flip-flop phase detector (PD) and passive loop filters including a programmable notch filter. To mitigate Delta Sigma quantization noise and PD nonlinearity effects, an FIR-filtered Delta Sigma modulation is employed for fractional division. The proposed bias-free fractional-N HPLL is implemented in 65nm CMOS. At 1.2GHz output, the phase noise of -97dBc/Hz at 1MHz offset frequency and the reference spur of -76dBc with the programmable notch filter are measured. When 14nm FinFET technology is used, simulation results show that a 1.2GHz bias-free PLL can be designed with a 0.4V supply.