Journal
2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
Volume -, Issue -, Pages -Publisher
IEEE
DOI: 10.1109/IEDM13553.2020.9372001
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Funding
- Ministry of Science and Technology [MOST-107-2221-E-492-016-MY3, 109-2923-E-492-001-MY3, 108-2622-8-002-016, 109-2634-F-009-029, 107-2628-E-492-001-MY3, 109-2923-E-492-002-MY3, 109-2222-E-492-002-MY3, 109-2628-E-492-001-MY3, 109-2636-E-006-004]
- JST, Japan [JPMJKB1902]
- Hitachi High-Technologies Corp. Japan
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For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 degrees C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration.
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