A 0.45/0.2-NEF/PEF 12-nV/√Hz Highly Configurable Discrete-Time Low-Noise Amplifier

This letter proposes a discrete-time low-noise amplifier (LNA) achieving a 0.45 noise efficiency factor (NEF) and 0.2 power efficiency factor (PEF), the lowest reported values to date. We demonstrate a switched-capacitor (SC)-based series-parallel amplifier (SPA) used as a noise-efficient LNA, relaxing the noise requirements of the following chain and reducing the power consumption of the analog frontend. A successive-approximation amplifier (SAA) serves as a second variable-gain stage. The proposed LNA achieves 1.2-mu VRMS inputreferred noise by oversampling the input signal while consuming 680 nW, including all the contributions from the clock-distribution network and gate drivers. The CMRR and PSRR are 97.1 dB and 78.6 dB, respectively, and the THD is -71 dB at 20-mVPP input.