Pearl: Performance-Aware Wear Leveling for Nonvolatile FPGAs

Since static random access memory (SRAM)-based field-programmable gate array (FPGA) has limited density and comparatively high leakage power, researchers have proposed FPGA architectures based on emerging nonvolatile memories (NVMs) to satisfy the requirements of data-intensive and low-power applications. Among all components, block random access memory (BRAM) has the severest endurance problem in FPGA. Unluckily, traditional wear leveling (TWL) strategies cannot be directly applied to nonvolatile FPGA because it may induce large performance overhead. In this article, we propose performance-aware wear leveling schemes for nonvolatile FPGA to improve its lifetime. Two strategies pertaining to coarse-grained wear leveling (C-Pearl) and fine-grained wear leveling (F-Pearl) are developed to balance inter-BRAM and intra-BRAM writes. Procedures, including static analysis, wear leveling-guided placement, and reconfiguration are discussed. A supportive circuit design is proposed, too. The evaluation shows that C-Pearl and F-Pearl can achieve 34% and 46% higher lifetime improvement and simultaneously 8% and 11% lower performance overhead than TWL.

Automated summary

This article proposes performance-aware wear leveling schemes for nonvolatile FPGA to improve its lifetime. Two strategies, coarse-grained wear leveling (C-Pearl) and fine-grained wear leveling (F-Pearl), are developed to balance inter-BRAM and intra-BRAM writes. Evaluation results show that C-Pearl and F-Pearl can achieve higher lifetime improvement and lower performance overhead compared to traditional wear leveling (TWL).