Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 68, Issue 5, Pages 2224-2233Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2021.3060880
Keywords
Parity check codes; Decoding; Throughput; Manganese; Parallel processing; Pipelines; Iterative decoding; Beyond-5G; THz communications; error control codes; LDPC; decoder; layered decoding
Categories
Funding
- EPIC project - European Union's Horizon 2020 Research and Innovation Program [760150]
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This paper proposes a multi-core architecture based on full row parallel layered LDPC decoder with frame interleaving, which increases the throughput by applying frame interleaving and using multi-core architectures. Two high rate medium size QC LDPC codes are designed and implemented with single core and multi-core architectures to explore different trade-offs. The multi-core decoder achieves the highest throughput for medium size LDPC codes and brings significant gains in area efficiency and energy efficiency compared to other high speed architectures.
Beyond 5G systems are expected to approach 1 Tb/s throughput. This poses a significant challenge to the channel decoder. In this paper, we propose a multi-core architecture based on full row parallel layered LDPC decoder with frame interleaving. Compared with conventional partially parallel layered architectures, the proposed architecture increases the throughput by applying frame interleaving into the pipeline architecture and by using multi-core architectures. Two high rate medium size QC LDPC codes are designed with fast decoding convergence speed for this architecture. Both codes are implemented with single core and multi-core architectures to explore different trade-offs between code design, communication performance and implementation. The four decoders are implemented in 16 nm CMOS FinFET technology with a clock rate of 1 GHz. The placement and routing implementation results show that the single core decoder for the LDPC (1027, 856) code is able to provide 114 Gb/s throughput at maximum 3 iterations with an area of 0.173 mm(2) and energy efficiency of 1.56 pJ/bit; the multi-core decoder for the (1032, 860) code is able to provide 860 Gb/s throughput at maximum 2 iterations with an area of 1.48 mm(2) and energy efficiency of 3.24 pJ/bit. The multi-core decoder achieves the highest throughput in the literature for medium size (1-2k) LDPC codes. When compared with other state-of-the-art fully parallel high speed architectures, the proposed architectures bring a significant gain both in area efficiency and energy efficiency while keeping the ability to offer flexibility in code rate, number of iterations and early stop.
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