Journal
IEEE TRANSACTIONS ON SIGNAL PROCESSING
Volume 69, Issue -, Pages 2971-2986Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TSP.2021.3064781
Keywords
Massive MIMO; matrix inversion; block diagonal matrix; Neumann series; FPGA; VLSI
Categories
Funding
- National Key R&D Program of China [2020YFB2205503]
- NSFC [61871115]
- Jiangsu Provincial NSF for ExcellentYoung Scholars [BK20180059]
- Six Talent Peak Program of Jiangsu Province [2018DZXX-001]
- Distinguished Perfection Professorship of Southeast University
- Fundamental Research Funds for the Central Universities
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This paper proposes a two-level and block diagonal based improved Neumann series approximation (TL-BD-INSA) algorithm, suitable for various channel conditions. The algorithm significantly reduces computational cost and achieves error-rate performance only 0.25 dB away from the exact method in non-ideal channel scenarios.
Massive multiple-input multiple-output (M-MIMO) brings better robustness and spectral efficiency but higher computational challenges compared to small-scale MIMO. One of the key challenges is the large-scale matrix inversion, as widely employed in channel estimation and detection. Traditionally, to address the issue, several low-complexity matrix inversion methods have been proposed, including the tri-diagonal matrix approximation (TMA) and the Neumann-series approximation (NSA). Although the previous methods effectively alleviate the computational cost, they all fail to exploit the typical properties of channel matrices, leading to unsatisfactory error-rate performance in some non-ideal scenarios. To solve the issue, in this paper, a two-level and block diagonal based improved Neumann series approximation (TL-BD-INSA) algorithm is proposed, which is suitable for both ideal uncorrelated channels and the correlated channels with multiple-antenna user equipment (MAUE) system. First, a two-level block diagonal iteration based on matrix partition is employed, which exhibits performance comparable to the exact method while having a lower computational load. An improved normalization factor is then introduced to accelerate convergence. Numerical results show that, for 128 x 32 MIMO with MAUE non-ideal channel, the proposed algorithm performs only 0.25 dB away from the exact matrix inversion when bit error rate (BER) = 10(-3). The implementation on Xilinx Virtex-7 FPGA and ASIC with TSMC 45 nm shows that the proposed detector can achieve 1731 bps/slices and 0.463 Gbps/mm(2) hardware efficiency, respectively, demonstrating that the proposed system can achieve a well trade-off between error performance and implementation efficiency.
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