Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

To overcome the von Neumann bottleneck, methods to compute in memory are being researched in many emerging memory technologies, including resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/IMPLY logic. In this work, we propose a method to implement a majority gate in a transistor-accessed ReRAM array during the READ operation. Together with NOT gate, which is also implemented in memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement the Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix (PP) adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how PP adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4.log(n)+6 for n-bit addition and is energy-efficient due to the absence of sneak currents in 1Transistor-lResistor configuration.

Automated summary

Traditional logic gates in computers are constructed using transistors, but this study proposes a method to implement majority gates and NOT gates in ReRAM memory, forming a complete Boolean logic capable of implementing any digital logic. By exploiting the proposed majority gate and the structure of the memory array, parallel-prefix adders can be implemented in memory, significantly reducing the latency of addition.