A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

In this paper, a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs), using the g(m)/I-D approach, is proposed for the Internet-of-things (IoT) scenario. The strategy optimizes the speed/dissipation of the OTA in terms of settling time, including slew-rate effects. It was designed for large capacitive loads and for transistors biased in the sub-threshold region, but it is also suitable for low-capacitive loads or for transistors biased in the saturation region. To validate the proposed strategy, a well-known three-stage OTA was designed starting from capacitive load and settling time requirements. Simulations confirmed that the OTA satisfies the specifications (even under Monte Carlo analysis), thus proving the correctness of the proposed approach.

Automated summary

This paper proposes a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs) for the Internet-of-things (IoT) scenario, optimizing speed/dissipation and suitable for various load and transistor biasing modes. Simulation results confirm the correctness of the proposed approach in meeting specifications, even under Monte Carlo analysis.