Journal
IEEE ELECTRON DEVICE LETTERS
Volume 42, Issue 7, Pages 994-997Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2021.3083219
Keywords
Ferroelectrics; hafnium zirconium oxide; ferroelectric memory; FeFET; endurance; reliability
Categories
Funding
- Berkeley Center for Negative Capacitance Transistors
- ASCENT Center, one of the six centers within the DARPA/SRC JUMP initiative
- DARPA FRANC program
- National Defense Science and Engineering Graduate Fellowship (NDSEG)
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Appropriate engineering of the interfacial layer can substantially improve the performance and reliability of FeFET devices.
We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding 1010 cycles. The ferroelectric transistors (FeFETs) incorporate a high-kappa interfacial layer (IL) of thermally grown silicon nitride (SiNx) and a thin 4.5 nm layer of Zr-doped FE-HfO2 (HZO) on a similar to 30 nm silicon on insulator (SOI) channel. The device shows a similar to 1V memory window (MW) in a DC sweep of just +/- 2.5V, and can be programmed and erased with voltage pulses of V-G = +/- 3V at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability.
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