4.6 Article

Topology design of digital metamaterials for ultra-compact integrated photonic devices based on mode manipulation

Journal

NANOSCALE ADVANCES
Volume 3, Issue 15, Pages 4579-4588

Publisher

ROYAL SOC CHEMISTRY
DOI: 10.1039/d1na00198a

Keywords

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Funding

  1. National Natural Science Foundation of China [61975123, 61671090]
  2. Fund of State Key Laboratory of Information Photonics and Optical Communications (Beijing University of Posts and Telecommunications), PR China [IPOC2020ZT01]

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This study demonstrates efficient mode conversion in silicon waveguides using digital metamaterials, providing a solution for all-optical interconnections in subwavelength functional regions. Satisfactory solutions, including conversions between six TE polarized modes, can be obtained with a small number of iterations.
Precise manipulation of mode order in silicon waveguides plays a fundamental role in the on-chip all-optical interconnections and is still a tough task in design when the functional region is confined to a subwavelength footprint. In this paper, digital metamaterials consisting of silicon and air pixels are topologically designed by an efficient method combining 2D finite element method for optical simulations, density method for material description and method of moving asymptotes for optimization. Only around 150 iterations are required for searching satisfactory solutions. Six high-quality and efficient conversions between four TE-polarized modes are achieved in a functional region with footprint 0.645 lambda(2) (center wavelength lambda = 1550 nm). Based on asymmetric mode conversion, a reciprocal optical diode with high contrast ratio is further obtained with the optimization starting from TE0-to-TE1 mode converter. Moreover, we successfully design a 1 x 2 demultiplexer with footprint 1.0 lambda(2) and demonstrate a simple mode division multiplexing system with satisfactory performances. Finally, by changing the refractive index to an equivalent value, quasi-3D designs are obtained and the functionalities are validated in 3D simulations for both free-standing and SOI configurations.

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