3.8 Proceedings Paper

Towards the Flexible and Efficient Implementation of the 5G-NR RAN Physical Layer

Journal

2021 IEEE RADIO AND WIRELESS SYMPOSIUM (RWS)
Volume -, Issue -, Pages 130-132

Publisher

IEEE
DOI: 10.1109/RWS50353.2021.9360353

Keywords

5G mobile communication; radio access networks; field programmable gate arrays; high level synthesis; digital signal processing

Funding

  1. European Regional Development Fund (FEDER)
  2. Competitiveness and Internationalization Operational Programme (COMPETE 2020) of the Portugal 2020 framework [024539, POCI-01-0247-FEDER-024539]

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This paper presents a flexible methodology to implement Fifth-Generation New Radio (5G-NR) Radio Access Network (RAN) lower entities, making use of a Field-Programmable Gate Array (FPGA) and a Radio Frequency (RF) front end, combining the Digital Signal Processing (DSP) techniques and the Software Defined Radio (SDR) technologies. The results show that the proposed method can meet the needs of 5G networks in terms of implementation, synchronization, and resource management.
This paper presents a flexible methodology to implement Fifth-Generation New Radio (5G-NR) Radio Access Network (RAN) lower entities, making use of a Field-Programmable Gate Array (FPGA) and a Radio Frequency (RF) front end, combining the Digital Signal Processing (DSP) techniques and the Software Defined Radio (SDR) technologies. The necessity of a fast and automated implementation flow is imposed by the diversity of the deployment scenarios and design options presented by the 5G networks. The proof-of-concept entity is the 5G-NR Distributed Unit (DU) receiver co-located with the Remote Unit (RU) receiver implemented in a ZCU102 evaluation kit and the integrated transceiver AD9371. This entity is in line with the needs of 5G networks and addresses issues of implementation, synchronization and resource management. The results show a resource usage of 25:7%, in which 4:4% belong to the 5G DU receiver and 21:3% to the AD9371 reference design, with a maximum operating frequency of 245.76 MHz and an Error Vector Magnitude (EVM) of 0:80%, providing the flexibility necessary to the instantiation of the transmitter part and multiple chains with different channel bandwidths, numerologies and design options.

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