Journal
IEEE ACCESS
Volume 9, Issue -, Pages 73121-73132Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/ACCESS.2021.3080310
Keywords
Hardware-based neural network; spiking neural network; flash memory synaptic device; AND type crossbar array; on-chip training; supervised learning; direct feedback alignment
Categories
Funding
- Technology Innovation Program by the Ministry of Trade, Industry and Energy (MOTIE), South Korea [20009972]
- Brain Korea 21 plus
- Korea Evaluation Institute of Industrial Technology (KEIT) [20009972] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
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The hardware-based neural network with thin-film transistor-type AND flash memory array architecture allows on-chip training and improves memory operation efficiency. The DFA algorithm enables efficient neural network design without the need for equal synaptic weights in the forward and backward paths. Additionally, pulse schemes tailored for the AND array architecture contribute to achieving high recognition accuracy in pattern learning tasks.
A hardware-based neural network that enables on-chip training using a thin-film transistor-type AND flash memory array architecture is designed. The synaptic device constituting the array is characterized by a doped p-type body, a gate insulator stack composed of SiO2/Si3N4/Al2O3, and a partially curved poly-Si channel. The body reduces the circuit burden on the high voltage driver required for both the source and drain lines when changing the synaptic weights. The high-kappa material included in the gate insulator stack helps to lower the operating voltage of the device. As the device scales down, the structural characteristics of the device have the potential to increase the efficiency of the memory operation and the immunity to the voltage drop effect that occurs in the bit-lines of the array. In an AND array architecture using fabricated synaptic devices, a pulse scheme for selective memory operation is proposed and verified experimentally. Due to the direct feedback alignment (DFA) algorithm, which does not need to have the same synaptic weight in the forward path and backward path, the AND array architecture can be utilized in designing an efficient on-chip training neural network. Pulse schemes suitable for the proposed AND array architecture are also devised to implement the DFA algorithm in neural networks. In a system-level simulation, a recognition accuracy of up to 97.01% is obtained in the MNIST pattern learning task based on the proposed pulse scheme and computing architecture.
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