Journal
PROCEEDINGS OF THE 2021 TWENTY SECOND INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2021)
Volume -, Issue -, Pages 103-108Publisher
IEEE
DOI: 10.1109/ISQED51717.2021.9424288
Keywords
Flash ADC; Offset Voltage; Order Statistics; On-chip Calibration; Clocked Comparator
Funding
- JSPS KAKENHI [19K20233]
- VDEC, The University of Tokyo
- Synopsys, Inc.
- Grants-in-Aid for Scientific Research [19K20233] Funding Source: KAKEN
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This study introduces a flash ADC architecture that reduces area and power consumption by utilizing offset voltage variations, successfully achieving a 5-bit ADC with power consumption of less than 1 mW at high speeds.
High-speed flash ADCs are required for wireless communication systems. However, the trade-off between area, power, and linearity suffers severely by offset voltage variation in sub-micron process. This paper proposes a flash ADC architecture that utilizes the offset voltage variation to reduce area and power consumption by eliminating reference generation. The proposed architecture utilizes offset voltages as references by selecting the appropriate comparators after an on-chip calibration. The on-chip calibration is performed based on order statistics that allows evaluating offset voltages in the time-domain. We verify our proposed architecture by HSPICE simulation based on a commercial 65 nm process. Our proposed architecture realizes a 5-bit ADC with the power consumption of less than 1 mW at 2 GS/s of operation, excluding the encoder.
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