Journal
2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)
Volume -, Issue -, Pages -Publisher
IEEE
DOI: 10.1109/IRPS46558.2021.9405128
Keywords
Single Event Upset; Logic Single Event Errors; FinFET Technology
Funding
- Soft Error Consortium
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Logic soft-error rates are predicted to surpass latch soft-error rates at advanced technology nodes due to higher operating frequencies. This research suggests an empirical method to estimate logic soft-error rates by using shift registers designed with conventional D flip-flops at the 7-nm node, providing valuable insights to designers during the design stages.
Logic soft-error rates are expected to exceed latch softerror rates at advanced technology nodes due to operating frequencies in the GHz range. Predictive models for logic soft-errors need difficult-to-obtain data for single-event transient pulse widths. This work proposes an empirical method for estimating logic soft-error rates using shift registers designed with conventional D flip-flops at the 7-nm node. Availability of this model will provide insight to designers on logic soft-error contributions during the design stages.
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