ESD-PCM: Constructing Reliable Super Dense Phase Change Memory Under Write Disturbance

Phase Change Memory (PCM) is an emerging Non-Volatile Memory (NVM) which has the characteristics of no data loss during power-off, generally no need to refresh, low power consumption, and high scalability. However, constructing super dense PCM based memory system will face Write Disturbance (WD) problem under 20nm technology node, which seriously affects data reliability and has become an urgent problem that should be solved. In this paper, we improve existing Super Dense Phase Change Memory (SD-PCM) scheme and propose Enhanced Super Dense Phase Change Memory (ESD-PCM) to mitigate WD errors in super dense PCM. ESD-PCM mainly includes the following three technical methods: first, Shared ECP based Correction makes more efficient use of Error-Correcting Pointers (ECP); second, Data Comparison based Read reduces latency, energy consumption, and space overhead during the process of Verify and Correct (VnC); third, Wear Leveling based (N:M)-Alloc achieves wear leveling and prolongs memory lifetime. Compared to basic VnC scheme, ESD-PCM reduces overhead and energy consumption by 13.7% and 14.5%, respectively. Moreover, ESD-PCM effectively reduces the probability of WD, enhances data reliability and improves system performance.

Automated summary

ESD-PCM is proposed to mitigate WD errors in super dense PCM by improving Shared ECP based Correction, Data Comparison based Read, and Wear Leveling based (N:M)-Alloc methods. Compared to basic VnC scheme, ESD-PCM reduces overhead and energy consumption by 13.7% and 14.5%, effectively reducing the probability of WD, enhancing data reliability and improving system performance.