Bayesian Optimization Approach for Analog Circuit Design Using Multi-task Gaussian Process

In this paper, we propose an efficient Bayesian optimization approach for analog circuit synthesis based on the multi-task Gaussian process model. Instead of building the Gaussian process models separately for each circuit specification as the traditional Bayesian optimization methods do, we extend the Gaussian process to a vector-valued function with a shared covariance function to learn the dependencies between different specifications of circuits. The weighted expected improvement function is selected as the acquisition function to cope with the constraints. The experimental results show that the proposed method can reduce the number of simulations while achieving better optimization results.

Automated summary

In this paper, an efficient Bayesian optimization approach for analog circuit synthesis is proposed using a multi-task Gaussian process model. By extending the Gaussian process to a vector-valued function with a shared covariance function, the method learns dependencies between different circuit specifications. The experimental results demonstrate that the proposed method can reduce the number of simulations needed while achieving better optimization results.