High-Efficient Nonbinary LDPC Decoder with Early Layer Decoding Schedule

Increasing nonbinary low density parity check (NB-LDPC) decoder throughput is challenging. This paper considers nonbinary quasi-cyclic LDPC code features to propose an early layered decoding schedule. The proposed method can eliminate idle time introduced by emptying pipeline stages after each layered decoding process, as well as increase decoder throughput. Layout results using TSMC 90-nm CMOS technology confirm that the proposed decoding schedule improved throughput with almost the same hardware complexity compared to the state-of-the-art NB-LDPC decoder. In particular, the proposed approach achieved considerably improved throughput and efficiency compared with predecessors when both early layer decoding schedule and early decoding termination were enabled.

Automated summary

This paper proposes an early layered decoding schedule based on nonbinary quasi-cyclic LDPC code features to increase decoder throughput. Experimental results using TSMC 90-nm CMOS technology demonstrate that the proposed decoding schedule improves throughput with almost the same hardware complexity compared to the state-of-the-art NB-LDPC decoder. In particular, significant improvements in throughput and efficiency are achieved when both early layer decoding schedule and early decoding termination are enabled.