3.8 Proceedings Paper

Bayesian optimization for Tuning Lithography Processes

Journal

IFAC PAPERSONLINE
Volume 54, Issue 7, Pages 827-832

Publisher

ELSEVIER
DOI: 10.1016/j.ifacol.2021.08.464

Keywords

Bayesian optimization; Process Tuning; Applications in Semiconductor Manufacturing

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This paper introduces a method for automatically optimizing lithography process parameters, which successfully improves the accuracy of process parameters and reduces process errors by using a Gaussian process-based Bayesian optimization method.
Lithography processes have advanced steps that need to be controlled accurately in order to achieve high production quality. The common approach is to have a setup phase in which the optimal parameters for each step of the process are explored manually by an operator. This paper introduces a process parameter selection system that can automate this exploration phase. Since a semiconductor manufacturing process is too complex to model mathematically as a whole, a model-based optimization technique is not preferred. Instead, a Gaussian process (GP) based Bayesian optimization (BO) method is applied to optimize the process parameters automatically. This method is designed according to the lithography process domain. To validate the performance of the GP based BO method, optimization experiments are run for eight different manufacturing processes. The results demonstrate that GP based BO obtains better process parameters that reduce the overlay error, an important quality metric, by 6.01% or 0.4 nm compared to the one achieved with the manual parameter selection process. Furthermore, the automated process parameter optimization requires much less expert user knowledge and can be completed in a shorter time. Considering the fact that the semiconductor manufacturers compete with each other with nanometric differences in features of their integrated circuit (IC) designs, this improvement could give a significant advantage in practical applications. Copyright (C) 2021 The Authors.

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