Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology

Emerging applications such as deep neural network demand high off-chip memory bandwidth. However, under stringent physical constraints of chip packages and system boards, it becomes very expensive to further increase the bandwidth of off-chip memory. Besides, transferring data across the memory hierarchy constitutes a large fraction of total energy consumption of systems, and the fraction has steadily increased with the stagnant technology scaling and poor data reuse characteristics of such emerging applications. To cost-effectively increase the bandwidth and energy efficiency, researchers began to reconsider the past processing-in-memory (PIM) architectures and advance them further, especially exploiting recent integration technologies such as 2.5D/3D stacking. Albeit the recent advances, no major memory manufacturer has developed even a proof-of-concept silicon yet, not to mention a product. This is because the past PIM architectures often require changes in host processors and/or application code which memory manufacturers cannot easily govern. In this paper, elegantly tackling the aforementioned challenges, we propose an innovative yet practical PIM architecture. To demonstrate its practicality and effectiveness at the system level, we implement it with a 20nm DRAM technology, integrate it with an unmodified commercial processor, develop the necessary software stack, and run existing applications without changing their source code. Our evaluation at the system level shows that our PIM improves the performance of memory-bound neural network kernels and applications by 11.2x and 3.5 x , respectively. Atop the performance improvement, PIM also reduces the energy per bit transfer by 3.5x, and the overall energy efficiency of the system running the applications by 3.2 x .

Automated summary

Emerging applications require high off-chip memory bandwidth, but it is costly to increase the bandwidth and transferring data across the memory hierarchy consumes a large amount of energy. To improve efficiency, researchers are revisiting past processing-in-memory architectures, especially leveraging recent integration technologies.