Journal
2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
Volume -, Issue -, Pages -Publisher
IEEE
DOI: 10.1109/ISCAS51556.2021.9401523
Keywords
Electrocardiography; QRS detection algorithm; field programmable gate arrays; wearable ECG sensors
Categories
Funding
- National Key Research and Development Program of China [2019YFB2204500]
- Science, Technology and Innovation Action Plan of Shanghai Municipality, China [1914220370]
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This paper proposed a resource-efficient 'QRS' detector with superior detection accuracy, utilizing a reconfigurable time-sharing computation unit and a position calibration unit based on data compression technique. The architecture achieved high sensitivity and precision, with significant reductions in computing resources, storage memory, and power consumption, outperforming state-of-the-art designs.
In this paper, we proposed a resource-efficient `QRS' detector with superior detection accuracy. Inspired by the strategy of the folded architecture, we adopted a reconfigurable time-sharing computation unit with a pipeline schedule. To further precisely locate the position of the 'R' peak and minimize the extra hardware cost, we designed the position calibration unit (PCU) based on the data compression technique. The proposed architecture was implemented on Xilinx Zynq-7000 with Verilog programming language. The proposed architecture achieves a sensitivity, Se of 99.76%, a precision, +P of 99.85%, and a detection error rate, DER of 0.40% on MIT-BIH database, which attains the best performance compared to state-of-the-art designs. Furthermore, the proposed architecture achieves a better hardware efficiency with 13 x, 1.28 x, and 4.35 x reductions in computing resources, storage memory, and power consumption, respectively.
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