Energy-Efficient Symmetrical Cascode OTA in a 130 nm CMOS Process

The analysis, design and experimental validation in a 130 nm CMOS process of a novel symmetrical cascode operational transconductance amplifier is presented. The amplifiers features very high energy efficiency thanks to the use of super class AB techniques, current starving and dynamic cascode biasing. The implementation of local common-mode feedback by two matched active resistors allows adaptation of the amplifier to the particular load employed, optimizing small-signal and large signal performance to such load. Measurements of a test chip prototype show an average slew rate of 6.3 V/mu s and a GBW of 7.53 MHz for a 120 pF load and a power consumption of 30 mu W.

Automated summary

A novel symmetrical cascode operational transconductance amplifier designed in a 130 nm CMOS process achieves high energy efficiency by utilizing super class AB techniques, current starving, and dynamic cascode biasing. The implementation of local common-mode feedback with two matched active resistors allows for optimization of small-signal and large signal performance for a specific load. Testing of a prototype chip demonstrates an average slew rate of 6.3 V/mu s and a GBW of 7.53 MHz for a 120 pF load, with a power consumption of 30 mu W.