Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices

We demonstrate, for the first time, Vertical-Transport Nanosheet (VTFET) CMOS logic transistors at sub-45nm gate pitch on bulk silicon wafers. We show that VTFETs present an opportunity to break the Contacted Gate Pitch (CGP) barrier faced by Lateral-Transport FETs. VTFETs offer scaling relief for electrostatics and parasitics by decoupling key device features from CGP-scaling roadblocks. First, nMOS/pMOS VTFET electrostatics are reported at sub-45nm gate pitch with SS = 69/68 mV/dec and sub-30mV DIBL. Well-behaved short channel characteristics with Si/SiGe source and drain are demonstrated in hardware. Symmetric device characteristics for SS and DIBL are achieved (with process optimization). Vertical nanosheets are utilized rather than vertical nanowires [1,2] for improved performance and area scaling. Functional ring oscillators demonstrate the excellent effective capacitance (Ceff) scaling advantages of VTFET nanosheets. Logic area scaling is furthered by use of Zero Diffusion Break (ZDB) isolation to eliminate dummy gates. Innovative I/O FET device design and hardware characteristics are shared.

Automated summary

Vertical-Transport Nanosheet (VTFET) CMOS logic transistors at sub-45nm gate pitch on bulk silicon wafers present a breakthrough in overcoming the Contacted Gate Pitch (CGP) barrier, offering scaling relief for electrostatics and parasitics. Innovative device characteristics and design strategies demonstrate improved performance and logic area scaling advantages.