A dynamic, compiler guided DVFS mechanism to achieve energy-efficiency in multi-core processors

Continuing progress and integration levels in silicon technologies make possible complete end-user systems on a single chip. This massive level of integration makes modern multi-core chips widely adoptable in multiple domains. In the design of high-performance massive multi-core chips, power and heat are dominant constraints. The increasing power consumption is of growing concern due to several reasons, e.g., cost, performance, reliability, scalability, and environmental impact. Increased power consumption not only raises chip temperature and cooling cost, but also decreases chip reliability and performance. Dynamic voltage and frequency scaling (DVFS) is a popular methodology to optimize the power usage/heat dissipation of electronic systems without significantly compromising overall system performance. The recent trend towards chip-multiprocessors (CMP) executing multi-threaded workloads with heterogeneous behavior motivates the need for per-core DVFS control mechanisms. In this paper, we propose a set of algorithms that use compile-time information to achieve DVFS control at run-time. By using compile-time information, we propose suitable heuristics, which make our power management mechanism more precise at run-time. We demonstrate that the proposed compiler-based DVFS mechanism performs better than the existing history- or profile-based methods that predict the future program behavior depending on the past statistics. (C) 2016 Published by Elsevier Inc.