Parallel Computation in the Racetrack Memory

Racetrack memories are promising candidates for next-generation solid-state storage devices. Various racetrack memories have been proposed in the literature, skyrmion based or domain wall based. However, none of them show integrated computing capabilities. Here, we introduce a new domain wall based racetrack concept that can operate both as a memory and as a computing device. The computation is defined by changing locally the anisotropy of the film. Stray fields from nearby cells are exploited to implement reconfigurable logic gates. We demonstrate that the racetrack array can operate in parallel in every cell. This is achieved by an external out-of-plane Zeeman field applied to the array. As proof-of-principle, we verified the single computing cell and multiple connected cells operating in parallel by micromagnetic simulations. Logic NAND/NOR is implemented independently in every computing cell. This study provides the guidelines for the development and optimization of this family of logic gates.

Automated summary

This study introduces a new domain wall-based racetrack concept that can operate as both a memory and a computing device, with reconfigurable logic gates implemented using stray fields from nearby cells. The racetrack array is shown to operate in parallel in every cell, with the potential for logic gates like NAND/NOR to be independently implemented in each computing cell.