Design-Time Exploration for Process, Environment and Aging Compensation Techniques for Low Power Reliable-Aware Design

Modern CMOS technologies such as advanced process FDSOI are affected by aging effects which can impact circuit functionality during lifetime operation. Indeed, due to system activity and usage dependence it is extremely difficult to establish a-priori sufficient guard bands for performance estimations, which leads either to large delay overestimation (and therefore loss of performances) or to reduced operating lifetime. In this paper, we propose an exploration of full adaptive AVS, ABB and combined supply and body bias techniques based on embedded monitors to obtain reliable functional operation, increased lifetime, while reducing the power consumption for the duration of the runtime. SPICE simulations performed on ARM processors show that large design margins in terms of area and power can be reduced, while keeping the target reliability and performance for the entire expected lifetime.

Automated summary

This paper explores the full adaptive AVS, ABB, and combined supply and body bias techniques based on embedded monitors to improve circuit reliability and lifetime while reducing power consumption. SPICE simulations on ARM processors show that large design margins in terms of area and power can be reduced, while maintaining target reliability and performance.