Journal
IEEE OPEN JOURNAL OF THE INDUSTRIAL ELECTRONICS SOCIETY
Volume 3, Issue -, Pages 339-352Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/OJIES.2022.3178042
Keywords
Phase locked loops; Voltage; Linear systems; Steady-state; Power system stability; Mathematical models; Analytical models; DDSRF-PLL; Linear Time Periodic; LVRT; small-signal stability; unbalanced system; voltage imbalance
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In this article, the LTI and LTP models of two different implementations of the DDSRF-PLL in the presence of voltage imbalance are analytically derived. The accuracy of the models is investigated through time domain simulations, frequency scans, and stability analysis. A guideline for selecting between LTI and LTP models for stability assessment of the DDSRF-PLL based on the degree of voltage imbalance is proposed. Additionally, it is discovered that the positive-sequence voltage can cause LTP dynamics depending on the DDSRF-PLL implementation, making the LTI model inaccurate even at low imbalance levels.
In this article, the Linear Time Invariant (LTI) and Linear Time Periodic (LTP) models of two different implementations of the DDSRF-PLL in the presence of voltage imbalance are derived analytically. The accuracy of the models is investigated with time domain simulations, frequency scans, and stability analysis. On top of this, a guideline for properly choosing between LTI and LTP models for stability assessment of the DDSRF-PLL according to the degree of grid voltage imbalance is proposed. Furthermore, it is revealed that, depending on the DDSRF-PLL implementation, the positive-sequence voltage might also cause LTP dynamics, rendering the LTI model inaccurate even when the imbalance is low.
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