Journal
IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS
Volume -, Issue -, Pages -Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNNLS.2022.3202501
Keywords
Neurons; Memristors; Task analysis; Synapses; Integrated circuit modeling; Biological neural networks; Unsupervised learning; Bienenstock-Cooper-Munro (BCM); memristor; resistive memory; spiking neural network (SNN); spike-timing-dependent plasticity (STDP)
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Artificial intelligence is changing computing by addressing real-world tasks and requiring significant memory access. This study proposes a neuro-synaptic architecture that integrates different learning rules to successfully solve two unsupervised learning tasks, using emerging memristive devices for low-latency and energy-efficient in-memory computing.
Artificial intelligence (AI) is changing the way computing is performed to cope with real-world, ill-defined tasks for which traditional algorithms fail. AI requires significant memory access, thus running into the von Neumann bottleneck when implemented in standard computing platforms. In this respect, low-latency energy-efficient in-memory computing can be achieved by exploiting emerging memristive devices, given their ability to emulate synaptic plasticity, which provides a path to design large-scale brain-inspired spiking neural networks (SNNs). Several plasticity rules have been described in the brain and their coexistence in the same network largely expands the computational capabilities of a given circuit. In this work, starting from the electrical characterization and modeling of the memristor device, we propose a neuro-synaptic architecture that co-integrates in a unique platform with a single type of synaptic device to implement two distinct learning rules, namely, the spike-timing-dependent plasticity (STDP) and the Bienenstock-Cooper-Munro (BCM). This architecture, by exploiting the aforementioned learning rules, successfully addressed two different tasks of unsupervised learning.
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