Journal
PROCEEDINGS OF 3RD IEEE CONFERENCE ON VLSI DEVICE, CIRCUIT AND SYSTEM (IEEE VLSI DCS 2022)
Volume -, Issue -, Pages 70-74Publisher
IEEE
DOI: 10.1109/VLSIDCS53788.2022.9811483
Keywords
Dual material double gate TFET; drain underlapping; parasitic capacitances; RF analysis; subthreshold slope
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This paper analyzes the DC and RF performance of a dual material double gate-drain underlapped tunnel FET (DMUDG TFET) and its channel pocketing variant (DMUDG-CP TFET). The study shows that these devices can deliver high ON current while maintaining the ambipolar current of a conventional TFET. The proposed structural engineering improves the subthreshold swing and optimizes the gate capacitance and gate-to-drain capacitance. The analysis of electrical characteristics reveals the potential of these devices in RF and low-power VLSI applications.
In this paper, the DC and RF performance of a dual material double gate-drain underlapped tunnel FET (DMUDG TFET) and a DMUDG TFET with channel pocketing (DMUDG-CP TFET) are analyzed. It has been shown in the work that the proposed devices delivered a high ON current without compromising the ambipolar current of a conventional DMDG TFET. The proposed structural engineering served the device to have a reasonably good subthreshold swing (SS) and optimize the gate capacitance and gate-to-drain capacitance. The electrical characteristics of the proposed devices are analyzed in terms of subthreshold swing, ambipolar current, intrinsic capacitances, cut-off frequency, and transconductance. The work aims to improve the analog performance of the proposed devices without forfeiting the digital performance much. A detailed simulation study of the proposed structures is performed using the Silvaco Atlas 2-D device simulator and compared with existing structures of contemporary literature. The study reveals that the proposed structures can be utilized in RF applications and low-power VLSI applications as well.
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