Journal
2019 19TH EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS (RADECS)
Volume -, Issue -, Pages 192-195Publisher
IEEE
DOI: 10.1109/RADECS47380.2019.9745693
Keywords
Zynq-7000 FPGA; Single Event Upsets (SEUs); Multiple Bit/Cell Upsets (MBUs/MCUs); Error Correction Codes (ECCs); Memory Scrubbing; Heavy Ion Irradiation
Funding
- European Space Agency (ESA)
- European Union
- Greek national funds through the Operational Program Competitiveness, Entrepreneurship and Innovation, under the call RESEARCH -CREATE -INNOVATE [T1EDK-04298]
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This paper presents a configuration memory scrubbing approach for the Xilinx Zynq-7000 devices. The approach combines the embedded Error Correction Code and an interframe parity scheme to detect and correct errors in the configuration memory. This methodology achieved 100% error correction coverage under heavy ion irradiation.
The paper presents a configuration memory scrubbing approach for the Xilinx Zynq-7000 devices. The approach combines the embedded Error Correction Code of the configuration memory frames and an interframe, interleaved parity scheme to form a mixed two-dimensional (2-D) error correction code. The 2-D coding scheme detects and corrects single and multiple bit upsets in the configuration memory of the Xilinx Zynq-7000 FPGA device. The proposed scrubbing methodology has been evaluated under heavy ion irradiation and achieved 100% error correction coverage.
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