Material Targets for Scaling All-Spin Logic

All-spin-logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to nonvolatility, ultralow operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin-logic devices that can surpass the energy-delay performance of CMOS transistors. With validated stochastic nanomagnetic and vector spin-transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identify promising directions for material engineering and discovery focusing on the systematic scaling of magnetic anisotropy (H-k) and saturation magnetization (M-s), the use of perpendicular magnetic anisotropy, and the interface spin-mixing conductance of the ferromagnet-spin-channel interface (G(mix)). We provide systematic targets for scaling a spin-logic energy-delay product toward 2 aJ ns, comprehending the stochastic noise for nanomagnets.