Endurance of 2 Mbit Based BEOL Integrated ReRAM

In this work, we experimentally characterize the endurance of 2 Mbit resistive switching random access memories (ReRAMs) from a 16 MBit test-chip. Here, very rare failure events where the memory cells become stuck in the low-resistive state (LRS) are observed. As this failure mechanism is the limiting one concerning the endurance of this ReRAM implementation, extensive investigations are conducted and presented. The experimental findings are detailed via a voltage divider model, illustrating why memory cells can become stuck in the LRS. It is proposed, that an insufficient voltage dropping over the cell due to an unfavorable combination of cell- and transistor resistances is responsible for stuck-at-LRS bits. Furthermore, predictions for the origin of these suboptimal combinations are given. Additionally, a one-dimensional Kinetic Monte Carlo (KMC) model that allows a statistical investigation of large numbers of cells with regard to rare random events has been developed. Here, our proposed explanation for the observed failure mechanism is fortified by the simulation and evaluation of the switching process of the memory. All simulations are in very good agreement with the experimental data. Finally, based on our findings, we give suggestions for the improvement of switching algorithms.

Automated summary

In this work, the endurance of 2 Mbit resistive switching random access memories (ReRAMs) from a 16 MBit test-chip is experimentally characterized. Rare failure events where the memory cells become stuck in the low-resistive state (LRS) are observed. Investigations, both experimental and simulation-based, are conducted to understand the underlying mechanisms causing the failure and provide suggestions for improving switching algorithms.