GraFF: A Multi-FPGA System with Memory Semantic Fabric for Scalable Graph Processing

FPGA has been a promising solution for graph processing in many scenarios. With a rapid growth in graph size, the on/off-chip memory capacity of a single FPGA is insufficient to hold large-scale graphs. To tackle such problem, in this position paper, we introduce GraFF, a Graph processing system with multiple FPGAs interconnected via a custom memory semantic Fabric. In order to efficiently exploit system parallelism, we first split the traversal of graph data into a series of independent fine-grained flits that are concurrently delivered among FPGAs as sheer memory semantic transactions. Then we relax FPGAs' synchronization from strict barrier boundaries between adjacent supersteps to fully parallelize graph traversing and computing. We build a prototype of GraFF with four custom FPGA nodes. Preliminary evaluation result based on the Breadth First Search (BFS) algorithm shows that the peak performance of GraFF reaches up to 6.23 GTEPS. Moreover, GraFF exhibits linear scalability when the number of FPGAs rises from one to four.

Automated summary

FPGA has shown great potential for graph processing, but the limited memory capacity of a single FPGA can be a challenge. In this paper, we propose GraFF, a graph processing system that connects multiple FPGAs via a custom memory semantic Fabric. By optimizing system parallelism and relaxing FPGA synchronization, GraFF achieves significant performance improvement and exhibits linear scalability as the number of FPGAs increases.