Journal
PRIME 2022: 17TH INTERNATIONAL CONFERENCE ON PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS
Volume -, Issue -, Pages 213-216Publisher
IEEE
DOI: 10.1109/PRIME55000.2022.9816775
Keywords
Formal verification; soft errors; single event upset; fault injection; hardware reliability
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This paper proposes a method for evaluating hardware reliability using formal methods, which can exhaustively search the entire state space and fault list in a reasonable time to assess system vulnerability.
Reliability is a major concern in many embedded systems. Redundancy-based methods are widely used against Single Event Upsets, causing significant temporal and spatial overhead. The traditional method to evaluate the reliability of a system is fault injection. However, it is practically impossible to test all faults for a complex design due to intractable simulation times. In this paper, we propose using formal methods to evaluate hardware reliability in the presence of soft errors. The proposed method can exhaustively search the entire state space and the whole fault list in a reasonable time. The method is applied to assess the vulnerability of all registers in a RISC-V Ibex core.
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