Journal
PRIME 2022: 17TH INTERNATIONAL CONFERENCE ON PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS
Volume -, Issue -, Pages 285-288Publisher
IEEE
DOI: 10.1109/PRIME55000.2022.9816829
Keywords
FPGA; Physically Unclonable Function; Programmable Delay Lines; Ring Oscillator
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Funding
- Diputacion General de Aragon [LMP197-21]
- Agencia Estatal de Investigacion [PID2020-114110RA-I00]
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In this paper, the performance of configurable physically unclonable functions based on ring oscillators (CRO-PUFs) implemented in FPGA is analyzed. The impact of differences in detailed routing at the LUT level is studied.
In this paper we analyze the performance of configurable physically unclonable functions based on ring oscillators (CRO-PUFs) implemented in FPGA due to differences in detailed routing at LUT level. The different PUF configurations for a given set of ring oscillators are generated using programmable delay lines on the cells realizing the inverters, while only one LUT input is used for the propagation of the oscillations along the ring. This architecture is suitable for implementation in FPGA, so the experiments have been conducted on Xilinx's Zynq SoC.
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