Improved Accuracy of the Power Hardware-in-the-Loop Modeling using Multirate Discrete Domain

Power Hardware-in-the-Loop (PHIL) enables realistic hardware testing interfacing with a simulated environment. The PHIL nature calls for power interfaces, such as analog-todigital converters, the power amplifier, and sensors, containing latency and noise. These elements are non-ideal, leading to inaccuracies and even instability. Accordingly, accurate modeling of a PHIL setup has become a challenging research topic. This paper presents accurate modeling of a PHIL setup approaching the actual hybrid analog/digital PHIL characteristics to ensure high accuracy in a wide frequency spectrum range. The proposed technique applies multirate discrete modeling, considering digital/analog sections as if in an actual setup. The accuracy is defined and evaluated over the frequency range of interests. The prominent voltage-type ideal transformer method (V-ITM) is employed as the interface algorithm. The proposed multirate discrete modeling is compared with purely continuous and singular discrete modeling approaches, considering all interface delays and dynamics while operating different hardware, namely, RL and RLC load. Frequency responses reveal a significant accuracy improvement in the proposed method. The step response similarly confirms the better performance of the proposed model in replicating the transients. The modeling methods are simulated using Simulink/MATLAB to confirm the validity of the proposed model.

Automated summary

This paper presents an accurate modeling approach for Power Hardware-in-the-Loop (PHIL) testing, aiming to improve the accuracy in a wide frequency spectrum range. The proposed technique utilizes multirate discrete modeling and considers interface delays and dynamics. Experimental results show that the proposed method performs better in terms of frequency response and step response.