3.8 Proceedings Paper

First Demonstration of Dual-Gated Indium Tin Oxide Transistors with Record Drive Current ∼2.3 mA/μm at L ≈ 60 nm and VDS=1 V

Journal

Publisher

IEEE
DOI: 10.1109/IEDM45625.2022.10019544

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Funding

  1. NSF [ECCS-2026822]
  2. Stanford SystemX Alliance
  3. Stanford Graduate Fellowship (SGF)

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This study reports the achievement of dual-gated indium tin oxide (ITO) transistors with record-high drive current and excellent electrical performance. By using Ni and Pd as contact layers and annealing to recover the threshold voltage, integration of dual-gated ITO transistors with high-kappa dielectrics is realized. Pd contacts show better performance and stability.
We report dual-gated indium tin oxide (ITO) transistors, with record-high drive current similar to 2.3 mA/mu m at channel length L similar to 60 nm and V-DS = 1 V. We explore both Ni and Pd as source and drain contacts to similar to 3.9 nm thin sputtered ITO channels before and after capping with similar to 10 nm HfO2, comparing back-gated transistor mobility, threshold voltage V-T, and contact resistance R-C. V-T shifts after capping are common for oxide transistors, but here we show how VT recovers by annealing at <= 300 degrees C in air. This enables us to achieve the first dual-gated ITO transistors with high-kappa HfO2 dielectrics, displaying high drive current, excellent on/off current ratio >= 10(8) and minimum subthreshold swing, SS similar to 70 mV/dec. Pd contacts have several advantages, including a more positive and consistent V-T with lower variability across all L, minimizing the V-T shift vs. L found for Ni contacts. Pd contacts also enable good R-C approximate to 300 Omega center dot mu m and effective mobility mu(eff) approximate to 41 cm(2)V(-1)s(-1). These results pave the way towards the back-end-of-line (BEOL) compatible integration of high performance, short-channel ITO transistors.

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