Related references
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Article
Engineering, Electrical & Electronic
Lilas Alrahis et al.
Summary: Hardware-based attacks on the semiconductor supply chain are on the rise, with logic locking serving as a promising design-for-trust scheme. Machine learning-based attacks are proving to be capable of breaking locking without needing an oracle, raising concerns about the security of logic locking. Our new oracle-less graph neural network-based attack, OMLA, shows superior performance compared to existing attacks in key-prediction accuracy on benchmark tests.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2022)
Article
Computer Science, Hardware & Architecture
Dominik Sisejkovic et al.
Summary: This article discusses the importance of logic locking techniques in protecting integrated circuits and addresses the security challenges posed by machine-learning-based attacks. It introduces a new scheme called D-MUX that is resilient against structure-exploiting machine learning attacks. The article also presents an evaluation of the cost of implementing D-MUX and claims it is the first machine-learning-resilient locking scheme. This work provides a starting point for future-generation logic locking in the era of machine learning.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2022)
Article
Computer Science, Hardware & Architecture
Sheikh Ariful Islam et al.
Summary: The research proposes three orthogonal techniques to secure Register-Transfer-Level (RTL) Intellectual Property (IP), including key-based RTL obfuscation, robust design lockout mechanism, and variants of the obfuscating module. These techniques demonstrate feasibility on ASIC and FPGA platforms for protecting data-path intensive IPs and crypto cores with different key lengths.
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
(2021)
Article
Computer Science, Hardware & Architecture
Dominik Sisejkovic et al.
Summary: This article introduces a new attack technique SnapShot that utilizes artificial neural networks to predict key bit values in logic locking with an average accuracy of 82.60%, representing a significant improvement over existing techniques. Evaluation results reveal vulnerabilities in common logic locking schemes and highlight the challenges of designing future logic locking schemes that are resilient to machine learning attacks.
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS
(2021)
Article
Computer Science, Hardware & Architecture
Christian Pilato et al.
Summary: This research proposes a new method called ASSURE to protect hardware IP modules operating on the register-transfer level (RTL) description, with multiple advantages.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
(2021)
Proceedings Paper
Computer Science, Artificial Intelligence
Lilas Alrahis et al.
Summary: Logic locking is a design-for-trust technique to protect design IP, but current attacks can circumvent secure techniques. GNNUnlock is a machine learning-based attack to break PSLL, successfully identifying protection logic without focusing on specific syntactic structures.
PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021)
(2021)
Proceedings Paper
Computer Science, Hardware & Architecture
Dominik Sisejkovic et al.
Summary: In the past decade, significant progress has been made in the design and evaluation of logic locking for safeguarding integrated circuits, while the rise of machine learning has introduced new ways to evaluate these schemes. This paper reviews recent advancements in logic locking attacks and countermeasures within the realm of contemporary machine learning models, highlighting key takeaways, opportunities, and challenges for developing next-generation logic locking techniques.
PROCEEDINGS OF THE 2021 IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC)
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Proceedings Paper
Automation & Control Systems
Md Rafid Muttaki et al.
Summary: This paper discusses the trust issues introduced to the integrated circuit supply chain by the horizontal business model in the semiconductor industry, and proposes a method for ensuring hardware protection by locking the design at a high-level description.
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(2021)
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(2017)
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2016)