☆ 3.8 Proceedings Paper

MLIR Loop Optimizations for High-Level Synthesis: a Case Study

PROCEEDINGS OF THE 2022 31ST INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PACT 2022 (2022)

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Journal

PROCEEDINGS OF THE 2022 31ST INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PACT 2022
Volume -, Issue -, Pages 544-545

Publisher

ASSOC COMPUTING MACHINERY
DOI: 10.1145/3559009.3569688

Keywords

FPGA; High-Level Synthesis; MLIR

Categories

Computer Science, Hardware & Architecture Computer Science, Software Engineering Computer Science, Theory & Methods

Funding

  1. PNNL Data-Model Convergence Laboratory-Directed RD Initiative
  2. DARPA RealTime Machine Learning (RTML) program
  3. P38 DoD/DOE collaboration
  4. H2020 EVEREST project [957269]
  5. H2020 HERMES project [101004203]

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