Journal
2023 IEEE RADIO AND WIRELESS SYMPOSIUM, RWS
Volume -, Issue -, Pages 61-63Publisher
IEEE
DOI: 10.1109/RWS55624.2023.10046322
Keywords
frequency synthesizer; direct digital synthesizer; interpolation; jitter; radio communication equipment
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This paper presents a new low-power ROM-less DDS with only a single current-switch array. The phase interpolator reduces the jitter in the accumulator overflow signal, achieving high frequency purity for the DDS. The self-adjusting two-step integrator generates ramp waves of appropriate amplitude automatically, eliminating the need to change the threshold voltage based on the clock frequency. This DDS reduces the required dual current-switch array in conventional phase interpolation DDSs, making it suitable for low-power consumption. The frequency purity of this DDS is tolerant to PVT variations.
This paper presents a new low-power ROM-less DDS with only a single current-switch array. The phase interpolator reduces the jitter contained in the accumulator overflow signal, so the DDS can obtain pulses with high frequency purity. The newly proposed self-adjusting two-step integrator automatically generates ramp waves of appropriate amplitude, eliminating the need to change the threshold voltage according to the clock frequency. Therefore, the dual current-switch array, which was required in the conventional phase interpolation DDSs, can be reduced by half, which is suitable for low power consumption. The frequency purity of this DDS is tolerant to PVT variations, because the manufacturing variation of the threshold voltage or unit current of the current-switch array is irrelevant to the phase interpolation operation. Experimental results confirm frequency synthesizer operation in which the spurious signal level is reduced to less than that of the accumulator.
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