Journal
IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS
Volume -, Issue -, Pages -Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LMWT.2023.3313168
Keywords
Fifth-generation; high power; single-pole double-throw (SPDT) switches; SOI CMOS; sub-6 GHz
Categories
Ask authors/readers for more resources
This letter presents a 0.5-4.5-GHz watt-level SPDT switch designed in 0.13-mu m CMOS SOI technology. By using stacked FETs with independent biasing, the power handling capacity of the switch is improved. The switch features low insertion loss and good isolation, making it suitable for the fifth-generation communication system.
This letter presents a 0.5-4.5-GHz (L-/S-band) watt-level single-pole double-throw (SPDT) switch in 0.13-mu m CMOS SOI technology from the GlobalFoundries (GF). This letter investigates the feasible methods to improve the power handling capacity of the FET switches circuits and analyzes the adopted structure of stacked FETs with independent biasing technique in detail. The proposed switch features 30.1-dBm OP1 dB at 3.5 GHz, better than 1.22-dB insertion loss (IL), and 33-dB isolation over the entire bandwidth, which meets the requirements of high-power handling of the fifth-generation communication system. The active chip area of the designed SPDT is compact with a size of only 0.78 x 0.38 mm(2).
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available