T3L: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure

The imminent rise in data consumption and the physical constraints of current advanced CMOS scaling hasten the end of the projection to the binary system. For a breakthrough of these issues, the ternary system, known for its superior efficiency in expressing numbers (closest to e approximate to 2.7183) has garnered considerable attention. Among the ternary studies reported, the anti-ambipolar transistor (AAT) is acquiring attention thanks to its unique negative differential resistance (NDR) and anti-ambipolar characteristics (AAC). Moreover, easy-to-fabricate inkjet-printing based AAT was introduced. Therefore, in this paper, we propose a practical design methodology ('(TL)-L-3 : The Tri-transistor Ternary Logic') and a set of novel ternary logic based on inkjet-printed AATs and CMOSs. In detail, 1) We propose balanced ternary full adders (BTFA) and prove that inkjet-printed AATs and CMOSs are highly capable of implementing any kind of ternary logic. 2) We propose two design methodologies for ternary logic design: NDR-based Design Method I and AAC-based Design Method II. 3) We present optimization methodology for inkjet-printed ternary circuit stability and provide circuitry to secure sufficient noise margin. We provide a highly-compact BTFA design that requires only

Automated summary

This paper presents a practical design methodology and a set of novel ternary logic based on inkjet-printed anti-ambipolar transistors (AATs) and CMOSs. Balanced ternary full adders and two design methodologies for ternary logic are proposed. Additionally, an optimization methodology for inkjet-printed ternary circuit stability is introduced.