Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume -, Issue -, Pages -Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2023.3315685
Keywords
GeSi; high-k gate stacks; highly stacked channels; nanosheets; nanowires; wet etching
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This study utilizes Hf(0.2)Zr(0.8)O(2) gate stacks with high dielectric constant to enhance the performance of high mobility Ge0.95Si0.05 channels, and achieves channel release through wet etching. Experimental results show that the ION of nanowires and nanosheets reach record high values under specific conditions, and gate delay can be improved by combining different structures.
By taking advantage of extremely high dielectric constant (kappa) of 47, the Hf(0.2)Zr(0.8)O(2 )gate stacks are integrated into the eight stacked high mobility Ge0.95Si0.05 channels with low thermal budget (<= 450 degrees C) to significantly enhance the I-ON. Isotropic wet etching by H2O2 and HNO3 serve well during the channel release of nanowires and nanosheets, respectively. The simulated kappa versus Zr concentration in HZO can show that the kappa can have a peak value at Zr concentration around 80%. The eight stacked Ge0.95Si0.05 nanowires and nanosheets with Hf0.2Zr0.8O2 gate stacks achieve the record high ION per footprint of 9200 mu A and record high ION per stack of 360 mu A at VOV = VDS = 0.5 V, respectively, among all Si/GeSi/Ge 3-D nFETs. Moreover, the potential gate delay improvement by combining the extremely high-kappa gate stacks and large floor number is studied by TCAD simulation using industrial device structures.
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