Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume -, Issue -, Pages -Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2023.3317778
Keywords
Analog integrated circuits; circuit theory; CMOS integrated circuits; high-speed integrated circuits; integrated circuit noise; microwave integrated circuits; radio frequency integrated circuits; switched capacitor circuits; wireless sensor networks
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This article presents a novel architecture for low-power RXs that achieves low power consumption, high sensitivity, and interferer tolerance. The proposed architecture performs well in terms of operating range, sensitivity, and power consumption.
Low-power receivers (RXs) with 100 mu W-scale power consumption can enable several power/energy-constrained Internet-of-Things (IoT) applications. However, achieving sensitivity, interferer tolerance, and wide operating range with low power presents a challenge for existing architectures, particularly those constrained to highly integrated solutions without high-QOFF-chip components. This article presents a low-power RX that utilizes a novel distributed N-path mixer architecture to enable asub-150-mu W multi-tone RX achieving wide operating range, high sensitivity and interferer tolerance. The proposed architecture is implemented in 22 nm CMOS and occupies 0.48 mm2. The RX achieves a 500-MHz operating range from 0.4 to 0.9 GHz with up to-85-dbm sensitivity for 100-kbps data rate with <150-mu Wpower consumption and up to -41-dB SIR tolerance.
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