Journal
ADVANCED MATERIALS
Volume -, Issue -, Pages -Publisher
WILEY-V C H VERLAG GMBH
DOI: 10.1002/adma.202308153
Keywords
memristors; retention time; single atoms materials; switching speed
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Memristor is a promising technology for future computing systems due to its low-power, high density, and scalability. However, there are still challenges to overcome, such as nonideal device characteristics. In this study, a high-performance memristor based on ITO/Ni single-atoms (NiSAs/N-C)/PVP/Au structure was developed, with improved switching speed and retention capability through the modulation of defect distribution and trapping level.
Memristor with low-power, high density, and scalability fulfills the requirements of the applications of the new computing system beyond Moore's law. However, there are still nonideal device characteristics observed in the memristor to be solved. The important observation is that retention and speed are correlated parameters of memristor with trade off against each other. The delicately modulating distribution and trapping level of defects in electron migration-based memristor is expected to provide a compromise method to address the contradictory issue of improving both switching speed and retention capability. Here, high-performance memristor based on the structure of ITO/Ni single-atoms (NiSAs/N-C)/Polyvinyl pyrrolidone (PVP)/Au is reported. By utilizing well-distributed trapping sites, small tunneling barriers/distance and high charging energy, the memristor with an ultrafast switching speed of 100 ns, ultralong retention capability of 10(6) s, a low set voltage (V-set) of approximate to 0.7 V, a substantial ON/OFF ration of 10(3), and low spatial variation in cycle-to-cycle (500 cycles) and device-to-device characteristics (128 devices) is demonstrated. On the premise of preserving the strengths of a fast switching speed, this memristor exhibits ultralong retention capability comparable to the commercialized flash memory. Finally, a memristor ratioed logic-based combinational memristor array to realize the one-bit full adder is further implemented.
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