Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume -, Issue -, Pages -Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2023.3333289
Keywords
Logic gates; Stress; Thin film transistors; Degradation; Temperature measurement; Tail; Semiconductor device measurement; Dynamic degradation; polycrystalline silicon (poly-Si); thin-film transistor (TFT); trap state
Ask authors/readers for more resources
This study investigates the degradation effects of different trap states on polycrystalline silicon thin-film transistors under alternating current gate pulse bias stress. It found that the decrease of ON-state current is the dominant degradation phenomenon, while acceptor-like trap states do not contribute to the degradation.
This article investigates the effects of different kinds of trap states on the degradation of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under alternating current (ac) gate pulse bias stress. P-type TFTs with different ON-state and subthreshold characteristics are fabricated, and thus, different distributions of donor-like tail states and deep states are achieved. The decrease of ON-state current is the dominant degradation phenomena for all the TFTs due to trap state generation occurring during the pulse rising edges. TFTs with higher donor-like trap states show severe degradation. It is attributed to the higher transient lateral electric field and hole concentration due to the higher donor-like deep state density, while acceptor-like trap states do not contribute to the degradation of p-type poly-Si TFTs under ac gate bias stress.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available