Efficient design approaches to model CNTFET-based Ternary Schmitt Trigger circuits

Digital computation using radix three offers the benefit of increased information density with less power consumption due to reduced interconnect complexity. Hence this brief presents two architectures for ternary Schmitt trigger designs that are implemented by combining shifting literals, ternary inverters and decoder equivalents using carbon nanotube technology. In the first proposed design, Schmitt trigger hysteresis curves are realized using shifting literals i.e. successor and predecessor cells. The second proposed design employs ternary inverters and a decoder equivalent of intermediate logic level for the implementation. The experimental analysis involves the simulations that are conducted using HSPICE and the standard Stanford CNTFET model. Simulation results confirm that the proposed ternary Schmitt trigger designs outperform in terms of power consumption and power delay product(PDP), showcasing the power reduction average of 75% and PDP reduction average of 79% respectively in comparison to recent counterparts. Moreover, Monte Carlo simulations are conducted to verify the robust operation of proposed designs and lesser deviations are observed in performance parameters towards process variations.

Automated summary

This article presents two architectures for ternary Schmitt trigger designs based on carbon nanotube technology. The proposed designs demonstrate superior performance in terms of power consumption and power delay product compared to similar designs, and show stability under process variations. These designs have the potential to achieve higher information density and lower power consumption in digital computation.