A status pre-matching method for the real-time simulation of power electronic converters

The inherent iterative problem limits the applicability of the resistance switch model in real-time simulation (RTS) for power electronic converters (PECs). This paper presents a status pre-matching method (SPM) that eliminates the iterative calculations for resistance switch model. The switch status can be easily and accurately determined by using gating signals and matching the switch resistances to the sign of the switch voltages. SPM can simulate all operation modes of PECs through a more convenient approach. Furthermore, a field program-mable gate array (FPGA) implementation scheme is proposed to fully utilize the multiplier units of FPGA. Finally, a three-phase back-to-back converter (3-ph BTBC) with 25 ns simulation time-step, 10 kHz switching frequency, as well as an LLC resonant converter with 17.2 ns simulation time-step, 100 kHz switching frequency, are implemented on FPGA. The results demonstrate the effectiveness and ability to reduce hardware resource con-sumption for SPM-based models.

Automated summary

This paper presents a status pre-matching method (SPM) that eliminates the iterative calculations for resistance switch model, and simulates all operation modes of PECs through a more convenient approach. Furthermore, a FPGA implementation scheme is proposed to fully utilize the multiplier units of FPGA.