Journal
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
Volume 69, Issue 1, Pages 101-108Publisher
ELSEVIER GMBH
DOI: 10.1016/j.aeue.2014.07.019
Keywords
Finite impulse response filter; Signed-power-of-two; Coefficient optimization; Differential evolution algorithm
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In this paper, we present a hardware efficient finite impulse response (FIR) filter design using differential evolution (DE) and common sub expression (CSE) elimination algorithm. With the DE algorithm, we first found a set of filter coefficients with reduced number of signed-power-of-two (SPT) terms without compromising on quality of the filter response. After obtaining coefficients, we applied CSE elimination algorithm, and determined the hardware cost in terms of adders. The filters were designed using DE for various word lengths, and the same were implemented in transposed direct form (TDF) structure. The implemented filters were synthesized in Cadence RTL compiler using UMC 90 nm technology. We compared the performances of our filters with recently best published works in terms of area, delay, power and power-delay-product (PDP). One of the proposed filters found to improve a PDP gain of 29% compared to Remez algorithm. The proposed approach showed improvements in filter design for the given specifications. (C) 2014 Elsevier GmbH. All rights reserved.
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