Low Power Analog Processing for Ultra-High-Speed Receivers With RF Correlation

Ultra-high-speed data communication receivers (Rxs) conventionally require analog digital converters (ADCs) with high sampling rates which have design challenges in terms of adequate resolution and power. This leads to ultra-high-speed Rxs utilising expensive and bulky high-speed oscilloscopes which are extremely inefficient for demodulation, in terms of power and size. Designing energy-efficient mixed-signal and baseband units for ultra-high speed, Rxs requires a paradigm approach, which is detailed in this paper, that circumvents the use of power hungry ADCs by employing low-power analog processing. The low-power analog Rx employs direct-demodulation with RF correlation using low-power comparators. The Rx is able to support multiple modulations with the highest modulation of 16-QAM reported so far for direct-demodulation with RF correlation. Simulations using Matlab, Simulink R2020a CIRCLED LATIN CAPITAL LETTER R indicate sufficient symbol-error rate (SER) performance at a symbol rate of 8 GS/s for the 71 GHz Urban Micro Cell and 140 GHz indoor channels. Power analysis undertaken with current analog, hybrid and digital beamforming approaches requiring ADCs indicates considerable power savings. This novel approach can be adopted for ultra-high-speed Rxs envisaged for beyond fifth generation (B5G)/sixth generation (6G)/ terahertz (THz) communication without power-hungry ADCs, leading to a low-power integrated design solution.

Automated summary

Ultra-high-speed data communication receivers conventionally require high-sampling-rate analog digital converters (ADCs) with design challenges in terms of resolution and power. However, this paper proposes a paradigm approach that circumvents the use of power-hungry ADCs by employing low-power analog processing. Through simulations using Matlab, a low-power analog Rx with direct-demodulation and RF correlation is able to support multiple modulations, including 16-QAM. Power analysis shows considerable power savings compared to other approaches requiring ADCs. This novel approach offers a low-power integrated design solution for ultra-high-speed communication.