4.7 Review

Processor power and energy consumption estimation techniques in IoT applications: A review

Journal

INTERNET OF THINGS
Volume 21, Issue -, Pages -

Publisher

ELSEVIER
DOI: 10.1016/j.iot.2022.100655

Keywords

Energy; Internet -of -Things; Power; Processor

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The energy efficiency of IoT nodes is crucial for effective IoT solutions, especially in the pursuit of carbon neutrality. This paper provides a comprehensive overview of processor power and energy consumption estimation techniques for researchers and IoT developers. The review covers methodologies for different abstraction levels and discusses the strengths and weaknesses of each technique. Future directions for estimation techniques development are also presented.
The energy efficiency of IoT nodes remains the dominant factor for effective IoT solutions that will meet the challenges of the 21st century, especially in the drive towards a carbon-neutral world through net-zero targets. Microprocessors/microcontrollers are devices that perform entire operations of IoT devices. Therefore, the power and energy consumption of these processors directly reflects the power consumed by the IoT devices they drive. An accurate estimation of the power and energy consumption of the processors is vital for the development of energyefficient IoT solutions because IoT devices are designed to operate in remote locations for long periods without human intervention. It is against this backdrop that this paper which is expected to serve as a guide for researches and IoT node/application developers in selecting the best technique for an IoT use-case, presents a review of processor power and energy consumption estimation techniques starting from the lowest level of abstraction to the highest level of abstraction. The review involves a detailed discussion of estimation technique methodologies for an abstraction level, and where applicable, generalized methodologies which cover the most approach used for an abstraction level are covered. The existence of overlaps and the impact of processor duty cycles on the techniques were discussed. A comparison of the strengths and weaknesses of each technique was made, from where register-transfer level and instruction level techniques are shown to be resilient against errors that occur from poor input signal conditioning. Future directions for the development of estimation techniques are also presented as recommendation.

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